In a ROM (Read Only Memory), switching devices such as MOS transistors are provided at intersections of row lines and column lines to store information as either a "1" or "0 ". As the integration density of such a ROM becomes higher, the impedance within the circuit also becomes higher, resulting in an increased parasitic capacitance. Accordingly, it is difficult to attain a higher speed together with a lower power consumption.
A high-speed readout technique for such a ROM was disclosed in Japanese Examined Patent Publication No. 46797/83 published on Oct. 18, 1983, for example. In accordance with this disclosed technique, a MOS transistor for precharging a column (X) line is provided between the column line and the power supply. When a change occurs in the address signal, a precharge signal having a constant duration is applied to the gate of such a MOS transistor to precharge the column line at a high speed. In driving a row line, it is pulled up only by a MOS transistor of depletion type which has a high impedance and which always stays in the conduction state. Accordingly, the operation of the MOS transistor comprising a memory cell for discharging the electronic charge is not hampered.
The maximum voltage on the column line of the above described prior art is the potential on the column (Y) line when row (X) lines which do not form memory cells are continuously selected. This voltage is nearly equal to the power supply voltage. And the lowest voltage on such a column (Y) line is low enough to be detected by a sense circuit. Since both precharge and discharge are monitored in the form of time, the voltage magnitude must have a sufficient allowance and it usually exceeds half of the power supply voltage. The voltage amplitude of the Y line is nearly half of the power supply voltage.